This invention relates generally to a non-volatile memory cell formed on the sidewall of a silicon pillar etched into a silicon substrate and the method of fabricating same. A vertical non-volatile memory cell and array are shown in Japanese Application No. 2-193153. This memory cell includes a drain region on top of a silicon pillar. The drain region includes a contact opening in the passivating dielectric for connection to a bit line for connection to other cells in the memory array. The dimension of the drain contact opening is the minimum line width of the process lithography. The contact opening lies entirely on the top surface of the silicon pillar. Therefore, the silicon pillar is required to be larger than the minimum lithographically definable diameter to account for the registration tolerance between the edge of the contact opening and the edge of the silicon pillar.
Furthermore, the bit line, which is conventionally an etched metal line, is required to overlap the edge of the drain contact opening to protect the underlying contact region. For this reason, the width of the bit line must be larger than the minimum definable line width. These requirements, resulting from the bit line contact opening lying entirely on the top surface of the pillar, result in a cell size that is larger than would be realized if the drain contact registration tolerances for the silicon pillar and metal bit line could be avoided.